`timescale 1ns/1ns
`define CHIP_CYCLE #10 // set one clk cycle to 10 time units
`define CHIP_HALF_CYCLE #5 // half a clock cycle
`define CHIP_RISE_CLK @(posedge clk)
`define CHIP_DEL #1

module bench;

   reg clk = 1;
   reg reset = 1;

   /*autoreginput*/
   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
   reg [63:0]		inst_i_line;		// To dut of ultraMips.v
   reg			inst_i_valid;		// To dut of ultraMips.v
   reg			mem_i_ctrl_m;		// To dut of ultraMips.v
   reg [4:0]		mem_i_dest_m;		// To dut of ultraMips.v
   reg [63:0]		mem_i_line;		// To dut of ultraMips.v
   reg [3:0]		mem_i_line_valid_m;	// To dut of ultraMips.v
   reg			resetn;			// To dut of ultraMips.v
   // End of automatics
   
   /*autowire*/
   // Beginning of automatic wires (for undeclared instantiated-module outputs)
   wire [31:0]		inst_o_addr;		// From dut of ultraMips.v
   wire			inst_o_valid;		// From dut of ultraMips.v
   wire [31:0]		mem_o_addr;		// From dut of ultraMips.v
   wire [1:0]		mem_o_ctrl;		// From dut of ultraMips.v
   wire [31:0]		mem_o_data;		// From dut of ultraMips.v
   wire [4:0]		mem_o_dest_reg;		// From dut of ultraMips.v
   wire [3:0]		mem_o_line_valid;	// From dut of ultraMips.v
   // End of automatics
   
   ultraMips dut (/*autoinst*/
		  // Outputs
		  .inst_o_valid		(inst_o_valid),
		  .inst_o_addr		(inst_o_addr[31:0]),
		  .mem_o_data		(mem_o_data[31:0]),
		  .mem_o_addr		(mem_o_addr[31:0]),
		  .mem_o_dest_reg	(mem_o_dest_reg[4:0]),
		  .mem_o_ctrl		(mem_o_ctrl[1:0]),
		  .mem_o_line_valid	(mem_o_line_valid[3:0]),
		  // Inputs
		  .clk			(clk),
		  .resetn		(resetn),
		  .inst_i_valid		(inst_i_valid),
		  .inst_i_line		(inst_i_line[63:0]),
		  .mem_i_line		(mem_i_line[63:0]),
		  .mem_i_dest_m		(mem_i_dest_m[4:0]),
		  .mem_i_ctrl_m		(mem_i_ctrl_m),
		  .mem_i_line_valid_m	(mem_i_line_valid_m[3:0]));

   // set up the clock
   always `CHIP_HALF_CYCLE clk = ~clk;

   initial
     begin
        $pli_init;
        $pli_drive;
        //$dumpfile("test.vcd");
        $dumpvars;
        
     end

   always @(posedge clk)
     begin
	`CHIP_DEL;
        /* capture outputs to pass on to C model */
        $pli_capture(inst_o_valid,
		     inst_o_addr,
		     mem_o_addr,
		     mem_o_data,
		     mem_o_dest_reg,
		     mem_o_ctrl,
		     mem_o_line_valid
		     );

        `CHIP_DEL;
        /* compare outputs to expected outputs, terminate on error */
        $pli_update;

        /* drive new inputs for the dut */
        $pli_drive(
		   reset,
		   inst_i_valid,
		   inst_i_line,
		   mem_i_line,
		   mem_i_dest_m,
		   mem_i_ctrl_m,
		   mem_i_line_valid_m,

		   ); 
     end
endmodule
// Local Variables:
// verilog-library-directories:("../rtl")
// verilog-library-extensions:(".v")
// End:

